As integrated circuits (ICs) are produced with greater and greater levels of circuit density, efficient methods for optimization of the designed circuits are needed. In any design, it is essential to optimize the testing of circuits, to meet the design criteria, as optimizing the circuits makes them compact and easily understandable and traceable. It also allows improved testing schemes that guarantee very high fault coverage while minimizing test costs.
Typically, ICs are presently designed by using high level languages and synthesized to achieve the Resistor Transistor Logic (RTL) level implementation. In most cases, the design implementation includes a number of redundant or non-active paths (false paths) and multi clock paths (MC Paths). All these constitute ‘do not care’ paths for the performance of the functional design. In a typical design, each path in the design is provided a constraint. During optimization, these paths are optimized individually based on the constraint associated to it. This is done prior to passing it to the design compiler to do the optimization and generate the net list. Since each path constraint has to be checked individually during optimization, the time taken for optimization is dependant on the number of paths with associated constraints. A typical prior art design flow 100 is shown in FIG. 1. The RTL design is provided typically to a design compiler 110 with the design criteria 101, to initially generate a set of constraints, optimize the path based on the constraints in the analyzer/optimizer 111, and then, using the synthesizer 112, generate a gate level design. This is then used to generate a design net list and associated constraints 113. This net list and constraints 113 are passed through functional test in the functional testing block 130, as well as into a static timing analyzer (STA) 150 to check if the design meets the design criteria. If not, a new set of requirements is generated to achieve the design criteria based on the output of functional testing block 130 or STA 150. The process of design compilation is repeated with constraint generation, followed by path optimization, and re-compilation using the new set of constraints. This is an iterative process of optimization, regeneration of constraints, generating the net list and running timing analysis in the STA 150 to verify the timing. The iterative process is run till the timing and other design criteria are met. Each time the synthesizer 110 is run, it provides inputs which are used to generate constraints and further attempts to optimize these paths. Hence, the number of paths and constraints play a large roll in the time taken for the optimization and synthesis of an IC.
In view of the limitations of the prior art, it will hence be advantageous to enable further reduction of the number of paths and constraints associated with a circuit at the RTL level, prior to using the design compiler, to reduce the time taken for optimization and make it more compact and readable. It will be further advantageous to reduce complexity by optimization for improving the performance, testability and traceability of the circuits.